The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of patterning dielectric layers for metal line formation and fabrication of metallization layers integrated circuits.
Metallization layers in integrated circuits allow for electrical connection between layers of integrated circuits and external devices. As circuit sizes have continued to shrink, new methods for patterning metallization layers and forming metallization lines continue to be developed to overcome limitations of existing fabrication equipment in meeting design requirements for newer and even smaller metal line features.